Trading Defect Tolerance for Chip Area in Nanotecnology Implementations of Systolic Arrays
Abstract
New self-assembling techniques used to build nano-scale architecture prototypes have a drawback of being prone to defects and transient faults. Fault and defect tolerance techniques will be crucial to the use of nano-electronics in the future. However, these techniques usually introduce a significant hardware overhead. In these paper we are proposing a method for trading an architecture tolerance on fabrication defects for chip area. The method will be presented using an architecture with generic topology and illustrated on the example of partially defect tolerant bit-plane semi-systolic array. In order to illustrate the method the results of FPGA implementation of completely fault tolerant bit-plane array, and partially fault tolerant bit-plane array will be given.
Source:
Proceedings of the Mediterranean Electrotechnical Conference - MELECON, 2012, 1083-1086Collections
Institution/Community
Mašinski fakultetTY - CONF AU - Cirić, Vladimir AU - Simić, Vladimir AU - Cvetković, Aleksandar AU - Milentijević, Ivan PY - 2012 UR - https://machinery.mas.bg.ac.rs/handle/123456789/1591 AB - New self-assembling techniques used to build nano-scale architecture prototypes have a drawback of being prone to defects and transient faults. Fault and defect tolerance techniques will be crucial to the use of nano-electronics in the future. However, these techniques usually introduce a significant hardware overhead. In these paper we are proposing a method for trading an architecture tolerance on fabrication defects for chip area. The method will be presented using an architecture with generic topology and illustrated on the example of partially defect tolerant bit-plane semi-systolic array. In order to illustrate the method the results of FPGA implementation of completely fault tolerant bit-plane array, and partially fault tolerant bit-plane array will be given. C3 - Proceedings of the Mediterranean Electrotechnical Conference - MELECON T1 - Trading Defect Tolerance for Chip Area in Nanotecnology Implementations of Systolic Arrays EP - 1086 SP - 1083 DO - 10.1109/MELCON.2012.6196616 ER -
@conference{ author = "Cirić, Vladimir and Simić, Vladimir and Cvetković, Aleksandar and Milentijević, Ivan", year = "2012", abstract = "New self-assembling techniques used to build nano-scale architecture prototypes have a drawback of being prone to defects and transient faults. Fault and defect tolerance techniques will be crucial to the use of nano-electronics in the future. However, these techniques usually introduce a significant hardware overhead. In these paper we are proposing a method for trading an architecture tolerance on fabrication defects for chip area. The method will be presented using an architecture with generic topology and illustrated on the example of partially defect tolerant bit-plane semi-systolic array. In order to illustrate the method the results of FPGA implementation of completely fault tolerant bit-plane array, and partially fault tolerant bit-plane array will be given.", journal = "Proceedings of the Mediterranean Electrotechnical Conference - MELECON", title = "Trading Defect Tolerance for Chip Area in Nanotecnology Implementations of Systolic Arrays", pages = "1086-1083", doi = "10.1109/MELCON.2012.6196616" }
Cirić, V., Simić, V., Cvetković, A.,& Milentijević, I.. (2012). Trading Defect Tolerance for Chip Area in Nanotecnology Implementations of Systolic Arrays. in Proceedings of the Mediterranean Electrotechnical Conference - MELECON, 1083-1086. https://doi.org/10.1109/MELCON.2012.6196616
Cirić V, Simić V, Cvetković A, Milentijević I. Trading Defect Tolerance for Chip Area in Nanotecnology Implementations of Systolic Arrays. in Proceedings of the Mediterranean Electrotechnical Conference - MELECON. 2012;:1083-1086. doi:10.1109/MELCON.2012.6196616 .
Cirić, Vladimir, Simić, Vladimir, Cvetković, Aleksandar, Milentijević, Ivan, "Trading Defect Tolerance for Chip Area in Nanotecnology Implementations of Systolic Arrays" in Proceedings of the Mediterranean Electrotechnical Conference - MELECON (2012):1083-1086, https://doi.org/10.1109/MELCON.2012.6196616 . .